System Validation by Source Level Emulation of Behavioral VHDL Specifications
نویسنده
چکیده
In this paper we present an approach to accelerate the simulation speed of behavioral VHDL system descriptions through the use of hardware support1. The method allows source level debugging of behavioral, algorithmic VHDL in a way similar to source level debugging known from software programming languages. We can set breakpoints in the source code and evaluate the contents of variables by reading the registers of the circuit when a breakpoint is reached.
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تاریخ انتشار 1995